What is considered for a prospective technique for improving the bit density of nonvolatile semiconductor memory devices such as NAND type flash memories is stacking of memory cells because miniaturizing techniques have almost come to their limit. As one example of the stacking technique, a stacked NAND type flash memory using memory transistors configured by vertical transistors is proposed. A stacked NAND type flash memory includes memory strings each configured by a plurality of memory transistors connected in series in the stacking direction, and select transistors provided at both ends of each memory string.
Such a stacked NAND type flash memory requires a control for suppressing erroneous writing into any memory transistors that are not the writing target.